VIT University

Applications are invited for Junior Research Fellow for DST funded project at the Power System Division School of Electrical Engineering, VIT University, Vellore.

Project Title: “Modeling, Analysis and Implementation of a Multilevel Multi-string Grid Tie Inverter for Medium Scale Grid Connected Photovoltaic System "  Number of Position: one  Position : Junior Research Fellow  Duration: 3 years  Qualification: Interested candidates should have an M.E/M.Tech (Electrical Engineering) with strong background in Power Systems and Power Electronics preferably qualified in GATE.  Desirable: 1. Good hands on experience with power electronic converters design.  2. Exposure on dSPACE 1103, Real Time Digital Simulator (RTDS) Matlab/ Simulink, real time workshop.  3. Self-independent and self-motivated 4. Very good mathematical background. Experience in Modeling Renewable Energy Systems is a great advantage (MPPT, Islanding, PLL etc.)  Fellowship: Rs. 16,000/-per month + 20% HRA for the first two years and Rs. 18,000/-per month+10% HRA for third year  Principal Investigator: Dr. Sarat Kumar Sahoo, Associate Professor, School of Electrical Engineering, VIT University, Vellore.  E-mail: sarata1@rediffmail.com Co-Principal Investigator: Dr. D. Vijay Kumar & Dr. S. Meikandasivam, School of Electrical Engineering, VIT University, Vellore. Interested candidates can send their CV with details of qualifications and latest passport size photo by post to Dr. Sarat Kumar Sahoo, Associate Professor, Room No. 532-F, Technology Tower, School of Electrical Engineering, VIT University, Vellore-632014, Tamilnadu, by post with a superscript on the envelope “Junior Research Fellow- DST” or by email tosarata1@rediffmail.com on or before November 15th 2014.