VIT University

Applications are invited for ‘Junior Research Fellow’ for DST Project in School of Electronics Engineering, VIT University, Chennai

Project Topic : Development of a Modelling Framework for Variability-Aware Design of Strained FinFET based Mixed Signal Circuits  Number of Positions: One  Duration: 3 years  Essential Qualifications: First Class M.E/M. Tech in VLSI Design/Microelectronics (or related research area). Preference will be given to candidates with GATE score.  Experience: One/Two years of experience in Nanoelectronics/VLSI Design may be desirable.  Fellowship: 25,000/- pm (consolidated)  Sponsoring Agency: SERB, DST, New Delhi  Last date for receipt of Application: 2nd May 2016 Interested candidates can send their CV (giving educational details, address for communication, e-mail and mobile number) along with supporting documents by post and/or e-mail to  Dr B. Bindu (Principal Investigator), Associate Professor, School of Electronics Engineering (SENSE), VIT University (Chennai Campus), Vandalur-Kelambakkam Road, Chennai-600127. Email: bindu.boby@vit.ac.in Short-listed candidates will be called for interview by phone or e-mail. Candidates must bring their original documents/supporting documents and their photocopy for interview. No TA/DA will be provided for attending the interview.